Since the development of the integrated circuit (IC), the semiconductor industry has experienced continued rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, these improvements in integration density have come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the area occupied by the integrated components is essentially on the surface of the semiconductor wafer. The increased density and corresponding decrease in area of the integrated circuit has generally surpassed the ability to bond an integrated circuit chip directly onto a substrate. Accordingly, interposers have been used to redistribute ball contact areas from that of the chip to a larger area of the interposer. Further, interposers have allowed for a three-dimensional (3D) package that includes multiple chips.
The redistribution of ball contact areas from that of the chip to a larger area of the interposer introduces high coefficient of thermal expansion (CTE) mismatch stress in the through vias of the interposer. This mismatch stress can cause defects in the interposer resulting in faulty interposers and ultimately unusable packages that include these faulty interposers. Accordingly, what is needed in the art is an improved packaging system.